(1) Field of the Invention
The present invention relates to a static-type semiconductor memory device and more particularly to a semiconductor memory device in which the length of time during which readout data is obtainable is increased and the reading out of data is reliably effected.
(2) Description of the Prior Art
Generally, in a semiconductor memory device, readout data is obtained by gating the output data from a sense amplifier with a strobe pulse after a predetermined time has passed since the time when new input address signals were input, i.e., when input address signals were changed. Therefore, it is desirable that the length of time during which readout data can be obtained by using a strobe pulse, i.e., during which the reading out of data is possible, be as long as possible.
FIG. 1 is a schematic diagram of the structure of a conventional static-type semiconductor memory device. In FIG. 1, MC designates a memory cell connected to a word line WL and bit lines BL and BL. Q.sub.1 and Q.sub.2 designate transistors, used as transfer gates, connected between the bit lines BL and BL and data buses DB and DB, respectively. RB is a row address buffer, RD is a row address decoder connected to the word line WL, CB is a column address buffer, CD is a column address decoder for driving the transistors Q.sub.1 and Q.sub.2 , SA is a sense amplifier connected to the data buses DB and DB, and OB is an output buffer.
In the structure of FIG. 1, when information is read out of the memory cell MC, row addres input signals RA.sub.IN and column address input signals CA.sub.IN are input into the row address buffer RB and the column address buffer CB, respectively, and, thereby, both the output signal of the row address decoder RD and the output signal of the column address decoder CD are rendered high. Thus, the potential of the word line WL becomes high and the memory cell MC is connected to the bit lines BL and BL. At this time, the transistors Q.sub.1 and Q.sub.2 are turned on and the bit lines BL and BL are connected to the data buses DB and DB, respectively. Therefore, the data signal from the memory cell MC is detected by the sense amplifier SA and is output as a data output signal D.sub.OUT after it is amplified by the output buffer OB.
Since a plurality of memory cells are connected to the word line WL, the time interval between the time when the address input signals are changed and the time when the output signal of the row address decoder, i.e., the potential of the word line WL, becomes high, is relatively long, as is illustrated in FIG. 2. The output of the column address decoder CD also rises a short time after the address input signals are changed. Therefore, the time interval between the time when the address input signals are changed and the time when the readout data D.sub.OUT is first available, varies from a time td.sub.1 to a time td.sub.2 , as shown in FIG. 2. In this case, the time td.sub.1 is the time period between the time when the address input signals are changed and the time when the output of the column address decoder CD rises and the transistors Q.sub.1 and Q.sub.2 are turned on. The time td.sub.1 corresponds to the data readout time in a case where the column addresses are changed but the row addresses are not changed. The time td.sub.2 corresponds to the data readout time in a case where both the column addresses and the row addresses are changed. Therefore, in the semiconductor memory device of FIG. 1, the time interval between the time when the address input signals are changed and the time when the readout data is first available, i.e., the data readout time varies from the time td.sub.1 to the time td.sub.2 , and the time interval t.sub.HOLD during which the readout data is made available by gating it with a strobe pulse, become relatively short, as is illustrated in FIG. 2.